A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

Mattias Palm; Daniele Mastantuono; Roland Strandberg; Lars Sundström; Sven Mattisson

doi:10.1109/ESSCIRC.2017.8094555

A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström, Sven Mattisson

Ericsson AB

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.

Originalspråk	engelska
Titel på värdpublikation	ESSCIRC 2017
Undertitel på värdpublikation	43rd IEEE European Solid State Circuits Conference
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (elektroniskt)	978-1-5090-5025-3
ISBN (tryckt)	978-1-5090-5026-0
DOI	https://doi.org/10.1109/ESSCIRC.2017.8094555
Status	Published - 2017
Externt publicerad	Ja
Evenemang	43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017 - Leuven, Belgien Varaktighet: 2017 sep. 11 → 2017 sep. 14

Konferens

Konferens	43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
Land/Territorium	Belgien
Ort	Leuven
Period	2017/09/11 → 2017/09/14

Ämnesklassifikation (UKÄ)

Annan elektroteknik och elektronik

Tillgång till dokument

10.1109/ESSCIRC.2017.8094555

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Palm, M., Mastantuono, D., Strandberg, R., Sundström, L., & Mattisson, S. (2017). A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI. I ESSCIRC 2017: 43rd IEEE European Solid State Circuits Conference IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2017.8094555

@inproceedings{5a90c0338c03462b8b09f628c23e0daa,

title = "A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI",

abstract = "This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.",

keywords = "buffer linearization, time-interleaved pipelined-SAR converter, multiband mobile communication receiver, super-source follower, drain bias resistor, sampling time mismatch, SFDR, gain mismatch correction, FD-SOI, input buffer, TI pipelined-SAR converter, specific bias current, common sample and hold circuit, SNR, SNDR, FOM, voltage references, bandgap, clock circuitry, subADC voltage reference",

author = "Mattias Palm and Daniele Mastantuono and Roland Strandberg and Lars Sundstr{\"o}m and Sven Mattisson",

year = "2017",

doi = "10.1109/ESSCIRC.2017.8094555",

language = "English",

isbn = "978-1-5090-5026-0",

booktitle = "ESSCIRC 2017",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017 ; Conference date: 11-09-2017 Through 14-09-2017",

}

Palm, M, Mastantuono, D, Strandberg, R, Sundström, L & Mattisson, S 2017, A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI. i ESSCIRC 2017: 43rd IEEE European Solid State Circuits Conference. IEEE - Institute of Electrical and Electronics Engineers Inc., 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgien, 2017/09/11. https://doi.org/10.1109/ESSCIRC.2017.8094555

A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI. / Palm, Mattias; Mastantuono, Daniele; Strandberg, Roland et al.
ESSCIRC 2017: 43rd IEEE European Solid State Circuits Conference. IEEE - Institute of Electrical and Electronics Engineers Inc., 2017.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

AU - Palm, Mattias

AU - Mastantuono, Daniele

AU - Strandberg, Roland

AU - Sundström, Lars

AU - Mattisson, Sven

PY - 2017

Y1 - 2017

N2 - This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.

AB - This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.

KW - buffer linearization

KW - time-interleaved pipelined-SAR converter

KW - multiband mobile communication receiver

KW - super-source follower

KW - drain bias resistor

KW - sampling time mismatch

KW - SFDR

KW - gain mismatch correction

KW - FD-SOI

KW - input buffer

KW - TI pipelined-SAR converter

KW - specific bias current

KW - common sample and hold circuit

KW - SNR

KW - SNDR

KW - FOM

KW - voltage references

KW - bandgap

KW - clock circuitry

KW - subADC voltage reference

U2 - 10.1109/ESSCIRC.2017.8094555

DO - 10.1109/ESSCIRC.2017.8094555

M3 - Paper in conference proceeding

SN - 978-1-5090-5026-0

BT - ESSCIRC 2017

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017

Y2 - 11 September 2017 through 14 September 2017

ER -

A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

Sammanfattning

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Ämnesklassifikation (UKÄ)

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