A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström, Sven Mattisson

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

2 Citeringar (SciVal)

Sammanfattning

This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.
Originalspråkengelska
Titel på värdpublikationESSCIRC 2017
Undertitel på värdpublikation43rd IEEE European Solid State Circuits Conference
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (elektroniskt)978-1-5090-5025-3
ISBN (tryckt)978-1-5090-5026-0
DOI
StatusPublished - 2017
Externt publiceradJa
Evenemang43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017 - Leuven, Belgien
Varaktighet: 2017 sep. 112017 sep. 14

Konferens

Konferens43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
Land/TerritoriumBelgien
OrtLeuven
Period2017/09/112017/09/14

Ämnesklassifikation (UKÄ)

  • Annan elektroteknik och elektronik

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