A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS

Reza Meraji; John B Anderson; Henrik Sjöland; Viktor Öwall

A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS

Reza Meraji, John B Anderson, Henrik Sjöland, Viktor Öwall

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.

Originalspråk	engelska
Titel på värdpublikation	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor	349-352
ISBN (tryckt)	978-1-4799-2452-3
Status	Published - 2013
Evenemang	2013 IEEE International Conference on Electronics, Circuits, and Systems - Abu Dhabi, U ARAB EMIRATES Varaktighet: 2013 dec. 8 → 2013 dec. 11

Konferens

Konferens	2013 IEEE International Conference on Electronics, Circuits, and Systems
Period	2013/12/08 → 2013/12/11

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

Citera det här

@inproceedings{ecddb403a9cc44178c3b710309555350,

title = "A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS",

abstract = "Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.",

author = "Reza Meraji and Anderson, {John B} and Henrik Sj{\"o}land and Viktor {\"O}wall",

year = "2013",

language = "English",

isbn = "978-1-4799-2452-3",

pages = "349--352",

booktitle = "2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2013 IEEE International Conference on Electronics, Circuits, and Systems ; Conference date: 08-12-2013 Through 11-12-2013",

}

Meraji, R, Anderson, JB , Sjöland, H & Öwall, V 2013, A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS. i 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 349-352, 2013 IEEE International Conference on Electronics, Circuits, and Systems, 2013/12/08.

A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS. / Meraji, Reza; Anderson, John B ; Sjöland, Henrik et al.

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE - Institute of Electrical and Electronics Engineers Inc., 2013. s. 349-352.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS

AU - Meraji, Reza

AU - Anderson, John B

AU - Sjöland, Henrik

AU - Öwall, Viktor

PY - 2013

Y1 - 2013

N2 - Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.

AB - Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.

M3 - Paper in conference proceeding

SN - 978-1-4799-2452-3

SP - 349

EP - 352

BT - 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 2013 IEEE International Conference on Electronics, Circuits, and Systems

Y2 - 8 December 2013 through 11 December 2013

ER -

A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS

Sammanfattning

Konferens

Ämnesklassifikation (UKÄ)

Fingeravtryck

Citera det här