A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Isael Diaz; Siyu Tan; Yun Miao; Leif Wilhelmsson; Ove Edfors; Viktor Öwall

doi:10.1109/ISCAS.2015.7169314

A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Isael Diaz, Siyu Tan, Yun Miao, Leif Wilhelmsson, Ove Edfors, Viktor Öwall

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

Correct estimation of symbol timing, Carrier Frequency
Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial
in Orthogonal Frequency Division Multiplexing (OFDM) communication.
Typically, high estimation accuracy is desired, but often
comes with increased complexity. Which has a direct repercussion
in energy consumption. In this article, an architecture based on
Sign-Bit estimation with low complexity, and hence low power
dissipation, is presented. The architecture, is capable of estimating
the afore-mentioned parameters in virtually any OFDM
standard. The proof of concept has been fabricated in 65 nm
CMOS technology with low-power high-VT cells. Measurements
performed with supply voltage of 1.2V. resulted in a power
dissipation of 350 μW, 6 times smaller to that of an equivalent
8-bit architecture, and the lowest power density reported in
literature.

Originalspråk	engelska
Titel på värdpublikation	2015 IEEE International Symposium on Circuits and Systems (ISCAS)
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (elektroniskt)	978-1-4799-8391-9
DOI	https://doi.org/10.1109/ISCAS.2015.7169314
Status	Published - 2015
Evenemang	IEEE International Symposium on Circuits and Systems (ISCAS), 2015 - Lisbon, Portugal Varaktighet: 2015 maj 24 → 2015 maj 27

Konferens

Konferens	IEEE International Symposium on Circuits and Systems (ISCAS), 2015
Land/Territorium	Portugal
Ort	Lisbon
Period	2015/05/24 → 2015/05/27

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

Tillgång till dokument

10.1109/ISCAS.2015.7169314

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@inproceedings{31be697a009346dd95d0143c09cf1feb,

title = "A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS",

abstract = "Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussion in energy consumption. In this article, an architecture based on Sign-Bit estimation with low complexity, and hence low power dissipation, is presented. The architecture, is capable of estimating the afore-mentioned parameters in virtually any OFDM standard. The proof of concept has been fabricated in 65 nm CMOS technology with low-power high-VT cells. Measurements performed with supply voltage of 1.2V. resulted in a power dissipation of 350 μW, 6 times smaller to that of an equivalent 8-bit architecture, and the lowest power density reported in literature.",

author = "Isael Diaz and Siyu Tan and Yun Miao and Leif Wilhelmsson and Ove Edfors and Viktor {\"O}wall",

year = "2015",

doi = "10.1109/ISCAS.2015.7169314",

language = "English",

booktitle = "2015 IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems (ISCAS), 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

}

Diaz, I, Tan, S, Miao, Y, Wilhelmsson, L, Edfors, O & Öwall, V 2015, A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS. i 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal, 2015/05/24. https://doi.org/10.1109/ISCAS.2015.7169314

A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS. / Diaz, Isael; Tan, Siyu; Miao, Yun et al.

2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., 2015.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

AU - Diaz, Isael

AU - Tan, Siyu

AU - Miao, Yun

AU - Wilhelmsson, Leif

AU - Edfors, Ove

AU - Öwall, Viktor

PY - 2015

Y1 - 2015

N2 - Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussion in energy consumption. In this article, an architecture based on Sign-Bit estimation with low complexity, and hence low power dissipation, is presented. The architecture, is capable of estimating the afore-mentioned parameters in virtually any OFDM standard. The proof of concept has been fabricated in 65 nm CMOS technology with low-power high-VT cells. Measurements performed with supply voltage of 1.2V. resulted in a power dissipation of 350 μW, 6 times smaller to that of an equivalent 8-bit architecture, and the lowest power density reported in literature.

AB - Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussion in energy consumption. In this article, an architecture based on Sign-Bit estimation with low complexity, and hence low power dissipation, is presented. The architecture, is capable of estimating the afore-mentioned parameters in virtually any OFDM standard. The proof of concept has been fabricated in 65 nm CMOS technology with low-power high-VT cells. Measurements performed with supply voltage of 1.2V. resulted in a power dissipation of 350 μW, 6 times smaller to that of an equivalent 8-bit architecture, and the lowest power density reported in literature.

U2 - 10.1109/ISCAS.2015.7169314

DO - 10.1109/ISCAS.2015.7169314

M3 - Paper in conference proceeding

BT - 2015 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems (ISCAS), 2015

Y2 - 24 May 2015 through 27 May 2015

ER -

A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Sammanfattning

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Ämnesklassifikation (UKÄ)

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