A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

Siyu Tan; Lars Sundstrom; Mattias Palm; Sven Mattisson; Pietro Andreani

doi:10.1109/NORCHIP.2019.8906969

A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

Siyu Tan, Lars Sundstrom, Mattias Palm, Sven Mattisson, Pietro Andreani

Ericsson AB

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.

Originalspråk	engelska
Titel på värdpublikation	2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019
Undertitel på värdpublikation	NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings
Redaktörer	Jari Nurmi, Peeter Ellervee, Kari Halonen, Juha Roning
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (elektroniskt)	9781728127699
ISBN (tryckt)	978-1-7281-2770-5
DOI	https://doi.org/10.1109/NORCHIP.2019.8906969
Status	Published - 2019 nov. 21
Evenemang	5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Helsinki, Finland Varaktighet: 2019 okt. 29 → 2019 okt. 30

Konferens

Konferens	5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019
Land/Territorium	Finland
Ort	Helsinki
Period	2019/10/29 → 2019/10/30

Ämnesklassifikation (UKÄ)

Signalbehandling

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10.1109/NORCHIP.2019.8906969

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1 Doktorsavhandling (sammanläggning)

High-Speed Analog-to-Digital Converters in CMOS
Tan, S., 2020 nov. 24, Lund University: Lund University, Faculty of Engineering. 200 s.
Forskningsoutput: Avhandling › Doktorsavhandling (sammanläggning)

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Tan, S., Sundstrom, L., Palm, M., Mattisson, S., & Andreani, P. (2019). A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. I J. Nurmi, P. Ellervee, K. Halonen, & J. Roning (Red.), 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings Artikel 8906969 IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NORCHIP.2019.8906969

Tan, Siyu ; Sundstrom, Lars ; Palm, Mattias et al. / A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. redaktör / Jari Nurmi ; Peeter Ellervee ; Kari Halonen ; Juha Roning. IEEE - Institute of Electrical and Electronics Engineers Inc., 2019.

@inproceedings{a40d6250be9447159cf8cbd60479cbaa,

title = "A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS",

abstract = "This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.",

author = "Siyu Tan and Lars Sundstrom and Mattias Palm and Sven Mattisson and Pietro Andreani",

year = "2019",

month = nov,

day = "21",

doi = "10.1109/NORCHIP.2019.8906969",

language = "English",

isbn = "978-1-7281-2770-5",

editor = "Jari Nurmi and Peeter Ellervee and Kari Halonen and Juha Roning",

booktitle = "2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 ; Conference date: 29-10-2019 Through 30-10-2019",

}

Tan, S, Sundstrom, L, Palm, M, Mattisson, S & Andreani, P 2019, A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. i J Nurmi, P Ellervee, K Halonen & J Roning (red), 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings., 8906969, IEEE - Institute of Electrical and Electronics Engineers Inc., 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019, Helsinki, Finland, 2019/10/29. https://doi.org/10.1109/NORCHIP.2019.8906969

A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. / Tan, Siyu; Sundstrom, Lars; Palm, Mattias et al.
2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. red. / Jari Nurmi; Peeter Ellervee; Kari Halonen; Juha Roning. IEEE - Institute of Electrical and Electronics Engineers Inc., 2019. 8906969.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

AU - Tan, Siyu

AU - Sundstrom, Lars

AU - Palm, Mattias

AU - Mattisson, Sven

AU - Andreani, Pietro

PY - 2019/11/21

Y1 - 2019/11/21

N2 - This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.

AB - This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.

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U2 - 10.1109/NORCHIP.2019.8906969

DO - 10.1109/NORCHIP.2019.8906969

M3 - Paper in conference proceeding

SN - 978-1-7281-2770-5

BT - 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019

A2 - Nurmi, Jari

A2 - Ellervee, Peeter

A2 - Halonen, Kari

A2 - Roning, Juha

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019

Y2 - 29 October 2019 through 30 October 2019

ER -

Tan S, Sundstrom L, Palm M, Mattisson S , Andreani P. A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS. I Nurmi J, Ellervee P, Halonen K, Roning J, redaktörer, 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc. 2019. 8906969 doi: 10.1109/NORCHIP.2019.8906969

A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS

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High-Speed Analog-to-Digital Converters in CMOS

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