A Floating-Point 16 × 16 SVD Accelerator for Beyond-5G Large Intelligent Surfaces

Beyond-5G wireless communication systems will feature advanced, key technologies such as large intelligent surfaces (LISs) composed of a very large number of antenna elements. The concomitant tremendous data rate requirements, due to the communication between these antennas, necessitate careful algorithm-architecture codesign. This paper presents an application-specific integrated circuit (ASIC) accelerator designed for efficient computation of singular value decomposition (SVD) utilized in distributed and scalable massive multiple-input multiple-output (MIMO) systems equipped with LISs. The design supports SVD calculation for 8 × 8 and 16 × 16 matrices and is synthesized using the GF -22nm fully depleted silicon-on-insulator (FD-SOI) technology with a clock frequency approaching 580 MHz. It takes up an area of 0.33 mm2 and consumes 219 mW of power. The system can pump out results at a cadence of 270/90 kSVDs/s, with a mean squared error (MSE) of 10-3, for 8 × 8 and 16 × 16 matrices, respectively.