A low complexity architecture for binary image erosion and dilation using structuring element decomposition

Hugo Hedberg; Fredrik Kristensen; Peter Nilsson; Viktor Öwall

doi:10.1109/ISCAS.2005.1465366

A low complexity architecture for binary image erosion and dilation using structuring element decomposition

Hugo Hedberg, Fredrik Kristensen, Peter Nilsson, Viktor Öwall

Institutionen för elektro- och informationsteknik

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log<sub>2</sub>(SE<sub>height</sub>), which means that a large span of SE sizes can be supported with a small amount of hardware

Originalspråk	engelska
Titel på värdpublikation	IEEE International Symposium on Circuits and Systems (ISCAS)
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor	3431-3434
ISBN (tryckt)	0-7803-8834-8
DOI	https://doi.org/10.1109/ISCAS.2005.1465366
Status	Published - 2005
Evenemang	IEEE International Symposium on Circuits and Systems (ISCAS), 2005 - Kobe, Japan Varaktighet: 2005 maj 23 → 2005 maj 26

Konferens

Konferens	IEEE International Symposium on Circuits and Systems (ISCAS), 2005
Land/Territorium	Japan
Ort	Kobe
Period	2005/05/23 → 2005/05/26

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

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10.1109/ISCAS.2005.1465366

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@inproceedings{35b6b579c3b04031b37611100e82d949,

title = "A low complexity architecture for binary image erosion and dilation using structuring element decomposition",

abstract = "This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log2(SEheight), which means that a large span of SE sizes can be supported with a small amount of hardware",

keywords = "structuring element decomposition, memory accesses per pixel, reduced memory requirements, power consumption, real-time surveillance system, image dilation, hardware architecture, low complexity architecture, binary image erosion",

author = "Hugo Hedberg and Fredrik Kristensen and Peter Nilsson and Viktor {\"O}wall",

year = "2005",

doi = "10.1109/ISCAS.2005.1465366",

language = "English",

isbn = "0-7803-8834-8",

pages = "3431--3434",

booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems (ISCAS), 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

}

Hedberg, H, Kristensen, F, Nilsson, P & Öwall, V 2005, A low complexity architecture for binary image erosion and dilation using structuring element decomposition. i IEEE International Symposium on Circuits and Systems (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., s. 3431-3434, IEEE International Symposium on Circuits and Systems (ISCAS), 2005, Kobe, Japan, 2005/05/23. https://doi.org/10.1109/ISCAS.2005.1465366

A low complexity architecture for binary image erosion and dilation using structuring element decomposition. / Hedberg, Hugo; Kristensen, Fredrik; Nilsson, Peter et al.

IEEE International Symposium on Circuits and Systems (ISCAS). IEEE - Institute of Electrical and Electronics Engineers Inc., 2005. s. 3431-3434.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - A low complexity architecture for binary image erosion and dilation using structuring element decomposition

AU - Hedberg, Hugo

AU - Kristensen, Fredrik

AU - Nilsson, Peter

AU - Öwall, Viktor

PY - 2005

Y1 - 2005

N2 - This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log2(SEheight), which means that a large span of SE sizes can be supported with a small amount of hardware

AB - This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log2(SEheight), which means that a large span of SE sizes can be supported with a small amount of hardware

KW - structuring element decomposition

KW - memory accesses per pixel

KW - reduced memory requirements

KW - power consumption

KW - real-time surveillance system

KW - image dilation

KW - hardware architecture

KW - low complexity architecture

KW - binary image erosion

U2 - 10.1109/ISCAS.2005.1465366

DO - 10.1109/ISCAS.2005.1465366

M3 - Paper in conference proceeding

SN - 0-7803-8834-8

SP - 3431

EP - 3434

BT - IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems (ISCAS), 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A low complexity architecture for binary image erosion and dilation using structuring element decomposition

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Ämnesklassifikation (UKÄ)

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