A low-complexity VLSI architecture for square root MIMO detection

Zhan Guo; Peter Nilsson

A low-complexity VLSI architecture for square root MIMO detection

Zhan Guo, Peter Nilsson

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

11 Citeringar (SciVal)

Sammanfattning

Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved

Originalspråk	engelska
Titel på värdpublikation	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
Förlag	ACTA Press
Sidor	304-309
ISBN (tryckt)	0-88986-351-2
Status	Published - 2003
Evenemang	IASTED International Conference on Circuits, Signals and Systems, 2003 - Cancun, Mexiko Varaktighet: 2003 maj 19 → 2003 maj 21

Konferens

Konferens	IASTED International Conference on Circuits, Signals and Systems, 2003
Land/Territorium	Mexiko
Ort	Cancun
Period	2003/05/19 → 2003/05/21

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@inproceedings{905439c552f141bdbb21f6a7677d2ab3,

title = "A low-complexity VLSI architecture for square root MIMO detection",

abstract = "Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved",

keywords = "multiple-input multiple-output, square root algorithm, power consumption, finite word length analysis, VirtexE series Xilinx FPGA, field programmable gate arrays, 4-transmit antennas, quarter phase-shift keying, 4-receive antennas, QPSK modulation, MIMO detection, VLSI architecture, very large scale integration",

author = "Zhan Guo and Peter Nilsson",

year = "2003",

language = "English",

isbn = "0-88986-351-2",

pages = "304--309",

booktitle = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",

publisher = "ACTA Press",

address = "Canada",

note = "IASTED International Conference on Circuits, Signals and Systems, 2003 ; Conference date: 19-05-2003 Through 21-05-2003",

}

TY - GEN

T1 - A low-complexity VLSI architecture for square root MIMO detection

AU - Guo, Zhan

AU - Nilsson, Peter

PY - 2003

Y1 - 2003

N2 - Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved

AB - Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved

KW - multiple-input multiple-output

KW - square root algorithm

KW - power consumption

KW - finite word length analysis

KW - VirtexE series Xilinx FPGA

KW - field programmable gate arrays

KW - 4-transmit antennas

KW - quarter phase-shift keying

KW - 4-receive antennas

KW - QPSK modulation

KW - MIMO detection

KW - VLSI architecture

KW - very large scale integration

M3 - Paper in conference proceeding

SN - 0-88986-351-2

SP - 304

EP - 309

BT - Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

PB - ACTA Press

T2 - IASTED International Conference on Circuits, Signals and Systems, 2003

Y2 - 19 May 2003 through 21 May 2003

ER -

A low-complexity VLSI architecture for square root MIMO detection

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