A low-complexity VLSI architecture for square root MIMO detection

Zhan Guo, Peter Nilsson

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

11 Citeringar (SciVal)

Sammanfattning

Low-complexity VLSI (very large scale integration) architecture of the square root algorithm is proposed for MIMO (multiple-input multiple-output) detection. As a modification to the traditional QR triangular array based architecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade-offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA (field programmable gate arrays). For a 4-transmit and 4-receive antennas MIMO system using QPSK (quarter phase-shift keying) modulation scheme, a detecting throughput of 80 Mb/s can be achieved
Originalspråkengelska
Titel på värdpublikationProceedings of the IASTED International Conference on Circuits, Signals, and Systems
FörlagACTA Press
Sidor304-309
ISBN (tryckt)0-88986-351-2
StatusPublished - 2003
EvenemangIASTED International Conference on Circuits, Signals and Systems, 2003 - Cancun, Mexiko
Varaktighet: 2003 maj 192003 maj 21

Konferens

KonferensIASTED International Conference on Circuits, Signals and Systems, 2003
Land/TerritoriumMexiko
OrtCancun
Period2003/05/192003/05/21

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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