A low latency and area efficient FFT processor for massive MIMO systems

Mojtaba Mahdavi; Ove Edfors; Viktor Öwall; Liang Liu

doi:10.1109/ISCAS.2017.8050692

A low latency and area efficient FFT processor for massive MIMO systems

Mojtaba Mahdavi, Ove Edfors, Viktor Öwall, Liang Liu

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.

Originalspråk	engelska
Titel på värdpublikation	IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor	1-4
Antal sidor	4
ISBN (elektroniskt)	978-1-4673-6853-7
ISBN (tryckt)	978-1-5090-1427-9
DOI	https://doi.org/10.1109/ISCAS.2017.8050692
Status	Published - 2017 maj 28
Evenemang	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, USA Varaktighet: 2017 maj 28 → 2017 maj 31

Konferens

Konferens	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Land/Territorium	USA
Ort	Baltimore
Period	2017/05/28 → 2017/05/31

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Kommunikationssystem

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10.1109/ISCAS.2017.8050692

1 Doktorsavhandling (sammanläggning)

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design
Mahdavi, M., 2021 mars 20, Dpt. of Electrical and Information Technology, Lund University, Sweden. 253 s.
Forskningsoutput: Avhandling › Doktorsavhandling (sammanläggning)

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@inproceedings{f617153af7fb44ff802ddbbbffced025,

title = "A low latency and area efficient FFT processor for massive MIMO systems",

abstract = "A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.",

keywords = "FFT, Massive MIMO, VLSI implementation, ASIC implementation, FPGA implementation, low latency, IFFT",

author = "Mojtaba Mahdavi and Ove Edfors and Viktor {\"O}wall and Liang Liu",

year = "2017",

month = may,

day = "28",

doi = "10.1109/ISCAS.2017.8050692",

language = "English",

isbn = "978-1-5090-1427-9",

pages = "1--4",

booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

}

Mahdavi, M, Edfors, O , Öwall, V & Liu, L 2017, A low latency and area efficient FFT processor for massive MIMO systems. i IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings., 8050692, IEEE - Institute of Electrical and Electronics Engineers Inc., s. 1-4, 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, USA, 2017/05/28. https://doi.org/10.1109/ISCAS.2017.8050692

A low latency and area efficient FFT processor for massive MIMO systems. / Mahdavi, Mojtaba; Edfors, Ove ; Öwall, Viktor et al.

IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings. IEEE - Institute of Electrical and Electronics Engineers Inc., 2017. s. 1-4 8050692.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - A low latency and area efficient FFT processor for massive MIMO systems

AU - Mahdavi, Mojtaba

AU - Edfors, Ove

AU - Öwall, Viktor

AU - Liu, Liang

PY - 2017/5/28

Y1 - 2017/5/28

N2 - A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.

AB - A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.

KW - FFT

KW - Massive MIMO

KW - VLSI implementation

KW - ASIC implementation

KW - FPGA implementation

KW - low latency

KW - IFFT

U2 - 10.1109/ISCAS.2017.8050692

DO - 10.1109/ISCAS.2017.8050692

M3 - Paper in conference proceeding

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BT - IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -

A low latency and area efficient FFT processor for massive MIMO systems

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Forskningsoutput

Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

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