A low-power 8-bit folding A/D converter with improved accuracy

Cheng Chen, Jiren Yuan

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

Sammanfattning

In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction
Originalspråkengelska
Titel på värdpublikation2006 8th International Conference on Solid-State and Integrated Circuit Technology
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Antal sidor4
ISBN (tryckt)1-4244-0160-7
DOI
StatusPublished - 2006
Evenemang2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, Kina
Varaktighet: 2006 okt. 232006 okt. 26

Konferens

Konferens2006 8th International Conference on Solid-State and Integrated Circuit Technology
Land/TerritoriumKina
OrtShanghai
Period2006/10/232006/10/26

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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