A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms

Daniel Piso Fernandez, Javier D. Bruguera

    Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

    Sammanfattning

    Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power performance (up to -24%).
    Originalspråkengelska
    Titel på värdpublikation2014 17th Euromicro Conference on Digital System Design (Dsd)
    FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
    Sidor639-642
    DOI
    StatusPublished - 2014
    Evenemang17th Euromicro Conference on Digital System Design (DSD) - Verona, ITALY
    Varaktighet: 2014 aug. 272014 aug. 29

    Konferens

    Konferens17th Euromicro Conference on Digital System Design (DSD)
    Period2014/08/272014/08/29

    Ämnesklassifikation (UKÄ)

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