Coarse grain clock gating of streaming applications in programmable logic implementations

Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn Janneck

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

13 Citeringar (SciVal)

Originalspråk	engelska
Titel på värdpublikation	[Host publication title missing]
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor	1-6
ISBN (tryckt)	979-10-92279-00-9
DOI	https://doi.org/10.1109/ESLsyn.2014.6850387
Status	Published - 2014
Evenemang	Electronic System Level Synthesis Conference (ESLsyn) - San Francisco, USA Varaktighet: 2014 maj 31 → 2015 juni 1

Konferens	Electronic System Level Synthesis Conference (ESLsyn)
Land/Territorium	USA
Ort	San Francisco
Period	2014/05/31 → 2015/06/01

Ämnesklassifikation (UKÄ)

@inproceedings{94cd457f84dc403895dd54f63edc5add,

title = "Coarse grain clock gating of streaming applications in programmable logic implementations",

author = "Endri Bezati and {Casale Brunet}, Simone and Marco Mattavelli and J{\"o}rn Janneck",

year = "2014",

doi = "10.1109/ESLsyn.2014.6850387",

language = "English",

isbn = "979-10-92279-00-9",

pages = "1--6",

booktitle = "[Host publication title missing]",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "Electronic System Level Synthesis Conference (ESLsyn) ; Conference date: 31-05-2014 Through 01-06-2015",

}

Bezati, E, Casale Brunet, S, Mattavelli, M & Janneck, J 2014, Coarse grain clock gating of streaming applications in programmable logic implementations. i [Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., s. 1-6, Electronic System Level Synthesis Conference (ESLsyn), San Francisco, USA, 2014/05/31. https://doi.org/10.1109/ESLsyn.2014.6850387

[Host publication title missing]. IEEE - Institute of Electrical and Electronics Engineers Inc., 2014. s. 1-6.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - Coarse grain clock gating of streaming applications in programmable logic implementations

AU - Bezati, Endri

AU - Casale Brunet, Simone

AU - Mattavelli, Marco

AU - Janneck, Jörn

PY - 2014

Y1 - 2014

U2 - 10.1109/ESLsyn.2014.6850387

DO - 10.1109/ESLsyn.2014.6850387

M3 - Paper in conference proceeding

SN - 979-10-92279-00-9

SP - 1

EP - 6

BT - [Host publication title missing]

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - Electronic System Level Synthesis Conference (ESLsyn)

Y2 - 31 May 2014 through 1 June 2015

ER -