Sammanfattning
We demonstrate for the first time a technology which allows the monolithic integration of both p-Type (InAs-Si) and n-Type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ∼70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS =-0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).
Originalspråk | engelska |
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Titel på värdpublikation | 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 |
Förlag | IEEE - Institute of Electrical and Electronics Engineers Inc. |
Volym | 2016-September |
ISBN (elektroniskt) | 9781509006373 |
DOI | |
Status | Published - 2016 sep. 21 |
Evenemang | 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, USA Varaktighet: 2016 juni 13 → 2016 juni 16 |
Konferens
Konferens | 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 |
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Land/Territorium | USA |
Ort | Honolulu |
Period | 2016/06/13 → 2016/06/16 |
Ämnesklassifikation (UKÄ)
- Annan elektroteknik och elektronik