Compressor design for silicon debug

Jing Zhang, Lars Johan Fritz, Liang Liu, Erik Larsson

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

Sammanfattning

The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.

Originalspråkengelska
Titel på värdpublikationProceedings - 2016 21st IEEE European Test Symposium, ETS 2016
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
ISBN (elektroniskt)9781467396592
DOI
StatusPublished - 2016 juli 22
Evenemang21st IEEE European Test Symposium, ETS 2016 - Amsterdam, Nederländerna
Varaktighet: 2016 maj 232016 maj 26

Konferens

Konferens21st IEEE European Test Symposium, ETS 2016
Land/TerritoriumNederländerna
OrtAmsterdam
Period2016/05/232016/05/26

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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