TY - JOUR
T1 - Cross-Point Arrays with Low-Power ITO-HfO2 Resistive Memory Cells Integrated on Vertical III-V Nanowires
AU - Persson, Karl-Magnus
AU - Mamidala, Saketh, Ram
AU - Kilpi, Olli-Pekka
AU - Borg, Mattias
AU - Wernersson, Lars-Erik
PY - 2020/5/11
Y1 - 2020/5/11
N2 - Vertical nanowires with cointegrated metal-oxide-semiconductor field-effect-transistor (MOSFET) selectors and nonvolatile resistive random access memory (RRAM) cells represent a promising candidate for fast, energy-efficient, cross-point memory cells. This paper explores indium-tin-oxide-hafnium-dioxide RRAM cells integrated onto arrays of indium-arsenide (InAs) vertical nanowires with a resulting area of 0.06 µm2 per cell. For low current operation, an improved switching uniformity over the intrinsic self-compliant behavior is demonstrated when using an external InAs nanowire MOSFET selector in series. The memory cells show consistent switching voltages below ±1 V and a switching cycle endurance of 106 is demonstrated. The developed fabrication scheme is fully compatible with low-ON-resistance vertical III-V nanowire MOSFET selectors, where operational compatibility with the initial high-field filament forming is established. Due to the small footprint of a vertical implementation, high density integration is achievable, and with a measured programming energy for 50 ns pulses at 0.49 pJ, the technology promises fast and ultralow power cross-point memory arrays.
AB - Vertical nanowires with cointegrated metal-oxide-semiconductor field-effect-transistor (MOSFET) selectors and nonvolatile resistive random access memory (RRAM) cells represent a promising candidate for fast, energy-efficient, cross-point memory cells. This paper explores indium-tin-oxide-hafnium-dioxide RRAM cells integrated onto arrays of indium-arsenide (InAs) vertical nanowires with a resulting area of 0.06 µm2 per cell. For low current operation, an improved switching uniformity over the intrinsic self-compliant behavior is demonstrated when using an external InAs nanowire MOSFET selector in series. The memory cells show consistent switching voltages below ±1 V and a switching cycle endurance of 106 is demonstrated. The developed fabrication scheme is fully compatible with low-ON-resistance vertical III-V nanowire MOSFET selectors, where operational compatibility with the initial high-field filament forming is established. Due to the small footprint of a vertical implementation, high density integration is achievable, and with a measured programming energy for 50 ns pulses at 0.49 pJ, the technology promises fast and ultralow power cross-point memory arrays.
KW - RRAM
KW - ITO
KW - Nanowires
KW - Memory arrays
U2 - 10.1002/aelm.202000154
DO - 10.1002/aelm.202000154
M3 - Article
AN - SCOPUS:85084449118
VL - 6
JO - Advanced Electronic Materials
JF - Advanced Electronic Materials
SN - 2199-160X
IS - 6
M1 - 2000154
ER -