Design considerations of a floating-point ADC with embedded S/H

Johan Piper, Jiren Yuan

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7 Citeringar (SciVal)

Sammanfattning

This paper presents the implementation and test results of a 10+5 bit 50 MS/s floating-point ADC, along with the design considerations. The combination of resistive weighting with identical chopped gain stages proved successful in gain, delay and offset matching. It demonstrated that the input referred thermal noise of the gain stages needs to aim for 15 bits, while the rest of the requirements such as channel matching (gain, delay, offset) and settling time need only 10 bits. The channel selecting logic has a serious impact on the ADC distortion, especially at high frequencies. For this reason, a robust channel selecting logic is suggested
Originalspråkengelska
Titel på gästpublikationIEEE International Symposium on Circuits and Systems (ISCAS)
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor6166-6169
ISBN (tryckt)0-7803-8834-8
DOI
StatusPublished - 2005
EvenemangIEEE International Symposium on Circuits and Systems (ISCAS), 2005 - Kobe, Japan
Varaktighet: 2005 maj 232005 maj 26

Konferens

KonferensIEEE International Symposium on Circuits and Systems (ISCAS), 2005
Land/TerritoriumJapan
OrtKobe
Period2005/05/232005/05/26

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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