Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation

Vertical nanowire MOSFETs exhibit asymmetric gate capacitances, allowing for their independent engineering to improve device high frequency performance. Minimizing gate-drain parasitic capacitance with the use of a vertical sidewall spacer enables universal feedback neutralization and a unilateral circuit design. For vertical spacer thickness above 20 nm, the gate-drain capacitance variability is reduced. Device technology is verified by simulation of 60 GHz three-stage low-noise amplifier. The amplifier exhibits 10 dB gain and 6.9 dB noise figure. The noise figure can be further reduced to 5.9 dB by combining several feedback techniques. The use of capacitance minimization reduces circuit sensitivity to device variation, demonstrating the potential of this technology in implementation of mm-wave communication and sensing systems.