Fabrication of next generation transistors calls for new technological requirements, such as reduced size and increased density of structures. Development of cost‐effective processing techniques to fabricate small‐pitch vertical III–V nanowires over large areas will be an important step toward realizing dense gate all‐around transistors, having high electron mobility, and low power consumption. It is demonstrated here, how arrays of III–V nanowires with a controllable number of rows, ranging from one single row up to bands of 500 nm, can be processed by directed self‐assembly (DSA) of block copolymer (BCP). Furthermore, it is shown that the DSA‐orientation with respect to the substrate's crystal direction affects the nanowire facet configuration, and thereby the nanowire spacing and gate all‐around deposition possibilities. A high χ poly(styrene)‐block‐poly(4‐vinylpyridine) BCP pattern directed by electron beam lithography‐defined guiding lines is transferred into silicon nitride. The silicon nitride is then used as a selective area metal‐organic vapor phase epitaxy mask atop an indium arsenide (InAs) buffer layer on a silicon platform to grow vertical InAs nanowires at 44–60 nm row pitch. Finally, deposition of high‐κ oxide and titanium nitride at this high pattern density is demonstrated, to further illustrate the considerations needed for next generation transistors. Directed self‐assembly of block copolymers is a cost‐effective technique suitable for high patterning densities. Here it is used to enable vertical III–V nanowire growth at ≈54 nm row pitch on a silicon platform in two different nanowire configurations. Furthermore, a path for gate all‐around deposition is explored, which could be of use for small footprint vertical transistor fabrication.
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