TY - JOUR
T1 - Energy Efficient Group-Sort QRD Processor with On-line Update for MIMO Channel Pre-processing
AU - Zhang, Chenxin
AU - Prabhu, Hemanth
AU - Liu, Yangxurui
AU - Liu, Liang
AU - Edfors, Ove
AU - Öwall, Viktor
PY - 2015
Y1 - 2015
N2 - This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, between the traditional brute-force SQRD and a proposed group-sort QR update strategy. A reconfigurable vector processor is accordingly developed to support the adaptive processing with high hardware efficiency. Furthermore, on-chip power management technique is also integrated to obtain real-time power-saving by adapting the voltage supply based on the instantaneous workload. As a proof-of-concept, we implemented the processor using a 65nm CMOS technology and conducted post-layout simulation. The proposed SQRD processor occupies 0.71mm2 core area and has a throughput of up to 69MQRD/s. Compared to the brute-force approach, an energy reduction of 10~61.8% is achieved.
AB - This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, between the traditional brute-force SQRD and a proposed group-sort QR update strategy. A reconfigurable vector processor is accordingly developed to support the adaptive processing with high hardware efficiency. Furthermore, on-chip power management technique is also integrated to obtain real-time power-saving by adapting the voltage supply based on the instantaneous workload. As a proof-of-concept, we implemented the processor using a 65nm CMOS technology and conducted post-layout simulation. The proposed SQRD processor occupies 0.71mm2 core area and has a throughput of up to 69MQRD/s. Compared to the brute-force approach, an energy reduction of 10~61.8% is achieved.
KW - QR decomposition
KW - sorting
KW - channel preprocessing
KW - MIMO
KW - reconfigurable processor
U2 - 10.1109/TCSI.2015.2402936
DO - 10.1109/TCSI.2015.2402936
M3 - Article
VL - 62
SP - 1220
EP - 1229
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 5
ER -