Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration

Stefan Granlund; Liang Liu; Chenxin Zhang; Viktor Öwall

doi:10.1109/NORCHIP.2013.6702034

Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration

Stefan Granlund, Liang Liu, Chenxin Zhang, Viktor Öwall

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

Sammanfattning

This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.

Originalspråk	engelska
Titel på värdpublikation	[Host publication title missing]
Antal sidor	4
DOI	https://doi.org/10.1109/NORCHIP.2013.6702034
Status	Published - 2013
Evenemang	NORCHIP Conference, 2013 - Vilnius, Litauen Varaktighet: 2013 nov. 11 → 2013 nov. 12

Konferens

Konferens	NORCHIP Conference, 2013
Land/Territorium	Litauen
Ort	Vilnius
Period	2013/11/11 → 2013/11/12

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

Tillgång till dokument

10.1109/NORCHIP.2013.6702034

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6702034&tag=1

HiPEC: High Performance Embedded Computing
Gruian, F., Kuchcinski, K., Janneck, J., Arslan, M. A., Mirza, U. M., Zhang, C., Cedersjö, G., Prabhu, H., Liu, L., Zhu, M., Liu, Y., Edfors, O. & Öwall, V.
Stiftelsen för Strategisk Forskning, SSF
2011/01/01 → 2015/12/31
Projekt: Forskning

Citera det här

@inproceedings{b22d1b7d20c548a3ae5dff521798ce1c,

title = "Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration",

abstract = "This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.",

author = "Stefan Granlund and Liang Liu and Chenxin Zhang and Viktor {\"O}wall",

year = "2013",

doi = "10.1109/NORCHIP.2013.6702034",

language = "English",

booktitle = "[Host publication title missing]",

note = "NORCHIP Conference, 2013 ; Conference date: 11-11-2013 Through 12-11-2013",

}

TY - GEN

T1 - Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration

AU - Granlund, Stefan

AU - Liu, Liang

AU - Zhang, Chenxin

AU - Öwall, Viktor

PY - 2013

Y1 - 2013

N2 - This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.

AB - This paper presents a high throughput, low latency soft-output signal detector for a 4×4 64-QAM MIMO system. To achieve high data-level parallelism and accurate soft information, the detector adopts a node perturbation technique to generate a list of candidate vectors around Zero Forcing, ZF, result. Additionally a fast and hardware friendly node enumeration scheme is developed to significantly reduce processing delay. Implemented using a 65nm CMOS technology, the detector occupies 0.58mm2 core area with 290K gates. The peak throughput is 3Gb/s at 500 MHz clock frequency with a latency of 20ns. Energy consumption per detected bit is 33pJ.

U2 - 10.1109/NORCHIP.2013.6702034

DO - 10.1109/NORCHIP.2013.6702034

M3 - Paper in conference proceeding

BT - [Host publication title missing]

T2 - NORCHIP Conference, 2013

Y2 - 11 November 2013 through 12 November 2013

ER -

Implementation of a Highly-Parallel Soft-Output MIMO Detector with Fast Node Enumeration

Sammanfattning

Konferens

Ämnesklassifikation (UKÄ)

Tillgång till dokument

Fingeravtryck

Projekt

HiPEC: High Performance Embedded Computing

Citera det här