A new architecture for Discrete Fourier Transform (DFT) based channel estimation has been analyzed, implemented and synthesized for ASIC. The core concept of the proposed esti- mation algorithm is to process the channel increments rather than the channel coefficients. With strong enough time correlation, we can reduce the wordlength of processing blocks compared to standard channel estimators and hence the resulting area and power. We provide an analytical tool to predict the potential gains in bit reduction for different mobility scenarios. Our simulations show that the wordlength can be reduced from 9 to 3 bits when operating in low mobility scenarios, with 5Hz Doppler frequency, while maintaining acceptable performance. Synthesis results show up to 40% reduction in area, compared to the original DFT-based approach, in a 65nm CMOS process.
|Titel på värdpublikation||[Host publication title missing]|
|Förlag||IEEE - Institute of Electrical and Electronics Engineers Inc.|
|Status||Published - 2014|
|Evenemang||SIPS 2014 - Belfast|
Varaktighet: 2014 okt. 20 → …
|Period||2014/10/20 → …|
- Elektroteknik och elektronik