Low power analog channel decoder in sub-threshold 65nm CMOS

Reza Meraji; John B Anderson; Viktor Öwall

Low power analog channel decoder in sub-threshold 65nm CMOS

Reza Meraji, John B Anderson, Viktor Öwall

Forskningsoutput: Konferensbidrag › Konferenspaper, ej i proceeding/ej förlagsutgivet

Sammanfattning

This paper presents the architecture and the corresponding
simulation results for a very low power half-rate
extended Hamming (8,4) decoder implemented in analog integrated
circuitry. TI’s 65nm low power CMOS design library
was used to simulate the complete decoder including an input
interface, an analog decoding core and an output interface. The
simulated bit error rate (BER) performance of the decoder is
presented and compared to the ideal performance expected from
the Hamming code. Transistor-level simulation results suggest
that a high throughput Hamming decoder up to 1 Mbits can be
implemented in analog circuits with a core power consumption
as low as 6 μW.

Originalspråk	engelska
Antal sidor	4
Status	Published - 2010
Evenemang	Swedish System-on-Chip Conference 2010 (SSoCC'10) - Kolmården, Sverige Varaktighet: 2010 maj 3 → 2010 maj 4

Konferens

Konferens	Swedish System-on-Chip Conference 2010 (SSoCC'10)
Land/Territorium	Sverige
Ort	Kolmården
Period	2010/05/03 → 2010/05/04

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

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@conference{67ad6381dc7b4797a61aebc89889b342,

title = "Low power analog channel decoder in sub-threshold 65nm CMOS",

abstract = "This paper presents the architecture and the corresponding simulation results for a very low power half-rate extended Hamming (8,4) decoder implemented in analog integrated circuitry. TI{\textquoteright}s 65nm low power CMOS design library was used to simulate the complete decoder including an input interface, an analog decoding core and an output interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance expected from the Hamming code. Transistor-level simulation results suggest that a high throughput Hamming decoder up to 1 Mbits can be implemented in analog circuits with a core power consumption as low as 6 μW.",

keywords = "sub-threshold CMOS, integrated circuits, low power circuits, Decoders",

author = "Reza Meraji and Anderson, {John B} and Viktor {\"O}wall",

year = "2010",

language = "English",

note = "Swedish System-on-Chip Conference 2010 (SSoCC'10) ; Conference date: 03-05-2010 Through 04-05-2010",

}

TY - CONF

T1 - Low power analog channel decoder in sub-threshold 65nm CMOS

AU - Meraji, Reza

AU - Anderson, John B

AU - Öwall, Viktor

PY - 2010

Y1 - 2010

N2 - This paper presents the architecture and the corresponding simulation results for a very low power half-rate extended Hamming (8,4) decoder implemented in analog integrated circuitry. TI’s 65nm low power CMOS design library was used to simulate the complete decoder including an input interface, an analog decoding core and an output interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance expected from the Hamming code. Transistor-level simulation results suggest that a high throughput Hamming decoder up to 1 Mbits can be implemented in analog circuits with a core power consumption as low as 6 μW.

AB - This paper presents the architecture and the corresponding simulation results for a very low power half-rate extended Hamming (8,4) decoder implemented in analog integrated circuitry. TI’s 65nm low power CMOS design library was used to simulate the complete decoder including an input interface, an analog decoding core and an output interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance expected from the Hamming code. Transistor-level simulation results suggest that a high throughput Hamming decoder up to 1 Mbits can be implemented in analog circuits with a core power consumption as low as 6 μW.

KW - sub-threshold CMOS

KW - integrated circuits

KW - low power circuits

KW - Decoders

M3 - Paper, not in proceeding

T2 - Swedish System-on-Chip Conference 2010 (SSoCC'10)

Y2 - 3 May 2010 through 4 May 2010

ER -

Low power analog channel decoder in sub-threshold 65nm CMOS

Sammanfattning

Konferens

Ämnesklassifikation (UKÄ)

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