Optimal System-on-Chip Test Scheduling

Erik Larsson, Hideo Fujiwara

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

Sammanfattning

In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts due to interconnection tests and (2) cases when a test limits an optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of an optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core, which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.
Originalspråkengelska
Titel på värdpublikation[Host publication title missing]
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor306-311
ISBN (tryckt)0-7695-1951-2
DOI
StatusPublished - 2003
Externt publiceradJa
Evenemang12th IEEE Asian Test Symposium ATS03 - Xi'an, Kina
Varaktighet: 2003 nov. 162003 nov. 19

Publikationsserier

Namn
ISSN (tryckt)1081-7735

Konferens

Konferens12th IEEE Asian Test Symposium ATS03
Land/TerritoriumKina
OrtXi'an
Period2003/11/162003/11/19

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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