Projekt per år
Sammanfattning
It is common for a system integrator to make use of third party intellectual property (IP) blocks from multiple vendors in the design of a circuit. These IPs may include test features, known as instruments, which are connected to a reconfigurable scan network, such as an IEEE Std. 1687 (IJTAG) network, for efficient on-chip integration and communication.
Using third party instruments this way becomes a security risk, since the instruments will have different levels of trust depending on the IP provider and intended use. In worst case, they may be malicious and directly harmful to the system. This paper provides security measures to protect a circuit from malicious instruments, attempting to perform data sniffing or data alteration attacks, within an IJTAG network. Security against these attacks is realized in the microarchitecture of segment insertion bit (SIB) components. The proposed solution provides easy integration into reconfigurable scan networks, where it was implemented on benchmark circuits and tested using commercial tools for test pattern generation and verification. Using the proposed solution in IJTAG networks results in very low area overhead, compatibility with existing test instructions and no added test time overhead, while maintaining compliance with IEEE Std. 1687.
Using third party instruments this way becomes a security risk, since the instruments will have different levels of trust depending on the IP provider and intended use. In worst case, they may be malicious and directly harmful to the system. This paper provides security measures to protect a circuit from malicious instruments, attempting to perform data sniffing or data alteration attacks, within an IJTAG network. Security against these attacks is realized in the microarchitecture of segment insertion bit (SIB) components. The proposed solution provides easy integration into reconfigurable scan networks, where it was implemented on benchmark circuits and tested using commercial tools for test pattern generation and verification. Using the proposed solution in IJTAG networks results in very low area overhead, compatibility with existing test instructions and no added test time overhead, while maintaining compliance with IEEE Std. 1687.
| Originalspråk | engelska |
|---|---|
| Titel på värdpublikation | 2025 IEEE European Test Symposium (ETS) |
| Förlag | IEEE - Institute of Electrical and Electronics Engineers Inc. |
| Antal sidor | 6 |
| Status | Published - 2025 maj 28 |
| Evenemang | 30th IEEE European Test Symposium - Tallinn, Estland Varaktighet: 2025 maj 26 → 2025 maj 29 https://ets2025.taltech.ee/ |
Konferens
| Konferens | 30th IEEE European Test Symposium |
|---|---|
| Land/Territorium | Estland |
| Ort | Tallinn |
| Period | 2025/05/26 → 2025/05/29 |
| Internetadress |
Ämnesklassifikation (UKÄ)
- Annan elektroteknik och elektronik
Fingeravtryck
Utforska forskningsämnen för ”Securing reconfigurable scan networks against data sniffing and data alteration attacks”. Tillsammans bildar de ett unikt fingeravtryck.Projekt
- 2 Aktiva
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Säkra system med komponenter från osäkra tillverkningskedjor
Larsson, E. (PI)
Swedish Government Agency for Innovation Systems (Vinnova)
2023/05/01 → 2026/04/30
Projekt: Forskning