Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Martin Berg; Karl-Magnus Persson; Olli-Pekka Kilpi; Johannes Svensson; Erik Lind; Lars-Erik Wernersson

doi:10.1109/IEDM.2015.7409806

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

Martin Berg, Karl-Magnus Persson, Olli-Pekka Kilpi, Johannes Svensson, Erik Lind, Lars-Erik Wernersson

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

248 Nedladdningar (Pure)

Sammanfattning

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

Originalspråk	engelska
Titel på värdpublikation	Technical Digest - International Electron Devices Meeting, IEDM
Förlag	IEEE - Institute of Electrical and Electronics Engineers Inc.
Volym	2016-February
ISBN (tryckt)	9781467398930
DOI	https://doi.org/10.1109/IEDM.2015.7409806
Status	Published - 2016 feb. 16
Evenemang	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, USA Varaktighet: 2015 dec. 7 → 2015 dec. 9

Konferens

Konferens	61st IEEE International Electron Devices Meeting, IEDM 2015
Land/Territorium	USA
Ort	Washington
Period	2015/12/07 → 2015/12/09

Ämnesklassifikation (UKÄ)

Elektroteknik och elektronik

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10.1109/IEDM.2015.7409806

IEDM_Proof_extended_abstract

1 Doktorsavhandling (sammanläggning)

Vertical III-V Nanowire MOSFETs
Kilpi, O.-P., 2019, Department of Electrical and Information Technology, Lund University. 90 s.
Forskningsoutput: Avhandling › Doktorsavhandling (sammanläggning)

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Berg, M., Persson, K.-M., Kilpi, O.-P., Svensson, J., Lind, E., & Wernersson, L.-E. (2016). Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. I Technical Digest - International Electron Devices Meeting, IEDM (Vol. 2016-February). Artikel 7409806 IEEE - Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409806

@inproceedings{ef8834bb39fb4a5090f298797f0ba7a8,

title = "Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si",

abstract = "In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.",

author = "Martin Berg and Karl-Magnus Persson and Olli-Pekka Kilpi and Johannes Svensson and Erik Lind and Lars-Erik Wernersson",

year = "2016",

month = feb,

day = "16",

doi = "10.1109/IEDM.2015.7409806",

language = "English",

isbn = "9781467398930",

volume = "2016-February",

booktitle = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "IEEE - Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",

}

Berg, M, Persson, K-M, Kilpi, O-P, Svensson, J , Lind, E & Wernersson, L-E 2016, Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. i Technical Digest - International Electron Devices Meeting, IEDM. vol. 2016-February, 7409806, IEEE - Institute of Electrical and Electronics Engineers Inc., 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, USA, 2015/12/07. https://doi.org/10.1109/IEDM.2015.7409806

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. / Berg, Martin; Persson, Karl-Magnus; Kilpi, Olli-Pekka et al.
Technical Digest - International Electron Devices Meeting, IEDM. Vol. 2016-February IEEE - Institute of Electrical and Electronics Engineers Inc., 2016. 7409806.

Forskningsoutput: Kapitel i bok/rapport/Conference proceeding › Konferenspaper i proceeding › Peer review

TY - GEN

T1 - Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

AU - Berg, Martin

AU - Persson, Karl-Magnus

AU - Kilpi, Olli-Pekka

AU - Svensson, Johannes

AU - Lind, Erik

AU - Wernersson, Lars-Erik

PY - 2016/2/16

Y1 - 2016/2/16

N2 - In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

AB - In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

U2 - 10.1109/IEDM.2015.7409806

DO - 10.1109/IEDM.2015.7409806

M3 - Paper in conference proceeding

AN - SCOPUS:84964040111

SN - 9781467398930

VL - 2016-February

BT - Technical Digest - International Electron Devices Meeting, IEDM

PB - IEEE - Institute of Electrical and Electronics Engineers Inc.

T2 - 61st IEEE International Electron Devices Meeting, IEDM 2015

Y2 - 7 December 2015 through 9 December 2015

ER -

Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

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Konferens

Ämnesklassifikation (UKÄ)

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Vertical III-V Nanowire MOSFETs

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