Spatially coupled serially concatenated codes (SC-SCCs) are constructed by coupling several classical turbo-like component codes. The resulting spatially coupled codes provide a close-to-capacity performance and low error ﬂoor, which have attracted a lot of interest in the past few years. The aim of this paper is to perform a comprehensive design space exploration to reveal different aspects of SC-SCCs, which is missing in the literature. More speciﬁcally, we investigate the effect of block length, coupling memory, decoding window size, and number of iterations on the decoding performance, complexity, latency, and throughput of SC-SCCs. Moreover, for the ﬁrst time, we demonstrate how to implement this class of codes in the hardware. To this end, we propose two decoding algorithms for the SC-SCCs along with the VLSI architectures. For each decoder architecture we investigate different implementation choices and accordingly evaluate the corresponding throughput, latency, and silicon area in a 12 nm FinFET technology. Finally, a design comparison followed by various design tradeoffs are presented.
|Tidskrift||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Status||Submitted - 2021 jul|
- Annan elektroteknik och elektronik