Supply-Voltage Down Conversion for Digital CMOS Designs

Peter Nilsson, Mohammed Azher Ali, Manivannan Ethiraj, Syed Muhammad Yasser Sherazi

Forskningsoutput: KonferensbidragKonferenspaper, ej i proceeding/ej förlagsutgivetPeer review

Sammanfattning

This paper presents a methodology to reduce the power consumption, by using multiple supply voltage levels. The voltage levels are scaled down from a single supply voltage, by the use of a diode-connected device. Only one single device is used per conversion, which gives a small area overhead. No inductors and no off-chip components are used. The methodology is tested on different constellations of inverters and on anti-aliasing filters. A power reduction down to 47% in the filters with reduced supply voltage and down to 72% in the complete filter is shown.
Originalspråkengelska
Antal sidor4
StatusPublished - 2014
EvenemangIEEE 21th International Conference on Electronics, Circuits and Systems, 2014 - Marseille, Frankrike
Varaktighet: 2014 dec. 72014 dec. 10

Konferens

KonferensIEEE 21th International Conference on Electronics, Circuits and Systems, 2014
Förkortad titelICECS 2014
Land/TerritoriumFrankrike
OrtMarseille
Period2014/12/072014/12/10

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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