Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

Breeta Sengupta, Erik Larsson

Forskningsoutput: Kapitel i bok/rapport/Conference proceedingKonferenspaper i proceedingPeer review

5 Citeringar (SciVal)
125 Nedladdningar (Pure)

Sammanfattning

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results
show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.
Originalspråkengelska
Titel på värdpublikationVLSI Test Symposium (VTS), 2014 IEEE 32nd
FörlagIEEE - Institute of Electrical and Electronics Engineers Inc.
Sidor1-6
Antal sidor6
DOI
StatusPublished - 2014
EvenemangIEEE VLSI Test Symposium (VTS) - Napa, CA, USA
Varaktighet: 2014 apr. 132014 apr. 17

Publikationsserier

Namn
ISSN (tryckt)1093-0167

Konferens

KonferensIEEE VLSI Test Symposium (VTS)
Land/TerritoriumUSA
OrtNapa, CA
Period2014/04/132014/04/17

Ämnesklassifikation (UKÄ)

  • Elektroteknik och elektronik

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