Vertical III-V Nanowire MOSFETs

Vertical III-V nanowire MOSFETs are interesting candidates for future digital and analog applications. High electron velocity III-V materials allow fabrication of low power and high frequency MOSFETs. Vertical vapor-liquid-solid growth enables fabrication of axial and radial heterostructure nanowires. This enables fabrication of novel structures where the band-gap can be engineered in the electron transport direction.

In this thesis, vertical InAs/InGaAs DC and RF MOSFETs on Si are fabricated and characterized. Several novel structures in vertical nanowire MOSFETs have been implemented such as gate-last process, axial/radial heterostructures, sub-30-nm gate-length, optimized RF design and field-plate structures. Several different nanowire compositions, such as InAs, InAs/In_0.7Ga_0.3As and InAs/In_0.4Ga_0.6As, were used. The radial heterostructureand the gate-last process enabled a record low access resistance in these devices. The axial heterostructure, on the other hand, allowed a wider band-gap material on the drain side, therefore suppressing the band-to-band tunnelling and impact ionization. This enabled a considerable improvement in the transistor off-state performance and for the first time I_off < 1 nA/µm was reported in non-planar In(Ga)As MOSFETs.

This work demonstrated several high performance devices, therefore highlighting the potential of the vertical nanowire MOSFETs. We demonstrate I_on = 407 mA/µm at I_off = 100 nA/µm and V_DD = 0.5 V, which is the highest reported I_on on vertical nanowire MOSFETs. We demonstrated g_m = 3.1 mS/µm, which is the highest demonstrated g_m on any MOSFET on Si. Further, we increased the breakdown voltage on InAs/InGaAs MOSFETs from 0.5 V to 2.5 V and demonstrated vertical nanowire MOSFETs with fT/ fmax > 100 GHz / 100 GHz.